Fault-Tolerant and Attack-Resistant Architectures Based on Programmable Devices: Research of Interplay and Common Features

About

Provider: GAČR (GA16-05179S)

Call name: 2015

Years: 2016-2018

Project Team

My Position: Team Member

Related publications

1. Belohoubek, J., Fiser, P., & Schmidt, J. (2016, August). Error Correction Method Based On The Short-Duration Offline Test. Euromicro Conference on Digital System Design (DSD), 2016. bibtex | manuscript | slides
2. Bělohoubek, J., Fišer, P., & Schmidt, J. (2017). Error masking method based on the short-duration offline test. Microprocessors and Microsystems, 52, 236–250. https://doi.org/10.1016/j.micpro.2017.06.007 bibtex | DOI | manuscript
   Cited by:
   1. Panek, R., Lojda, J., Podivinsky, J., & Kotásek, Z. (2018). Partial Dynamic Reconfiguration in an FPGA-based Fault-Tolerant System: Simulation-based Evaluation. 2018 IEEE East-West Design & Test Symposium (EWDTS), 1–6.
   2. Cananzi, D. A., Van Hartingsveldt, E. B., & Romain, M. (2020). Logic buffer for hitless single event upset handling. Google Patents.
      US Patent 10,565,048
3. Belohoubek, J., Fiser, P., & Schmidt, J. (2019, April). Using Voters May Lead to Secret Leakage. 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2019). bibtex | manuscript | poster
   Cited by:
   1. Jagadesh, T., Remya, V., Jaishankar, B., & Murugan, K. (2021). Analysis of Static Power Reduction Techniques in Shift Registers. In Advances in Mechanical Engineering (pp. 567–577). Springer.