Photoelectric Laser Stimulation of Combinational Logic

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CMOS structures evaluation (e.g. conventional gates or majority voter) under Photoelectric Laser Stimulation (PLS)

Project Web: https://github.com/DDD-FIT-CTU/CMOS-PLS/

Related publications

1. Bělohoubek, J., Fišer, P., & Schmidt, J. (2021). Optically induced static power in combinational logic: Vulnerabilities and countermeasures. Microelectronics Reliability, 124, 114281. https://doi.org/10.1016/j.microrel.2021.114281 bibtex | DOI | manuscript
   Cited by:
   1. Kumar, A., Tripathi, S. L., & Subramaniam, U. (2021). Variability Analysis of SBOX With CMOS 45 nm Technology. Wireless Personal Communications.
   2. Tebina, N.-E. O., Zergainoh, N.-E., Hubert, G., & Maistri, P. (2023). Simulation Methodology for Assessing X-Ray Effects on Digital Circuits. 2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 1–6. https://doi.org/10.1109/DFT59622.2023.10313564 | DOI